This addition process starts by adding bits a0 and b0 then in the next clock cycle bits a1 and b1 are added, which is also added with the carry from the bit position '0' and so on. Let us consider A = an–1 an–2….a0 and B = bn–1 bn–2 ….b0 are the two unsigned numbers that has to be added to produce the sum S = Sn–1,Sn-2….So. Figure show the block diagram for the serial adder The counter counts down to 'o' and then stops and disables further changes in the output shift register. When the circuit is reset the counter is loaded with the number of bits in the serial adder i.e. It also includes a down counter to determine when the adder should halted be cause all 'n' bits of the required sun are present in the output shift register. The shift registers are loaded with parallel data when the circuit is reset. In serial adder three shift registers are used for the inputs A and B and the output sum. Serial adder consists of the shift registers and the adder FSM.
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